Plans for the second DAQ column prototype

Column with PC-based RU

HW components

RU

• PC to run SW RU Done.
• Generic III card as data generator and RUI Done.
• bricolage to input the trigger signal to the GIII Done. Do we still want a second TTCrx?
• Later the TTCrx with the GIII could act as a more realistic FED emulator.
• Myrinet NIC as RUO

BU + EVM

• PC to run as BU and EVM Done.
• Myrinet NIC in BU as input
• TTCrx with adapter Done.

Trigger system

• TTCvi in a VME crate Done.
• VME PPC to control TTCvi -> Use SBS PCI-VME interface instead. Done.
• some NIM logic to implement trigger generator and veto Done.
• Later a GIII could act as a GTP

SW components

• TTCvi driver - trigger control Done.
• TTCrx driver - poll trigger info Done. Occasional errors still.
• NIC firmware - point-to-point transport layer for XDAQ -> try GM first.
• GIII firmware - data generator Done.
• HW access library Done.
• DAQ user toolkit Done.
• EVM Done.
• RU Done.
• BU Done.
• Run control GUI (java) - start from the last one -> use xdaqWin and RCMS instead. Cancelled. RCMS still has missing features.

Implementation plan

1. Run new XDAQ on all PCs Done.
2. Run new XDAQ on VME PPC -> Use SBS. Done.
3. Trigger generator NIM logic Done.
4. Trigger through TTCvi Done.
5. GUI control -> use xdaqWin and RCMS instead. Cancelled
6. Read out TTCrx Done.
7. Veto from TTCrx Done.
8. Generate data Done.
9. Veto from GIII Done.
10. Data into RU Done.
11. Data out of RU Done.
12. Data into BU Done.
13. Data transfer using Myrinet
14. Performance measurements
15. Simulate multiple RU/BU messaging

Extension possibilities

• Separate data generation from RU (LVDS or Myrinet link)
• Separate EVM from BU (RCN or Myrinet switch)
• Add FUs after BU
• Integrate as one leg of the EVB demonstrator
• Emulate Global Trigger Processor using GIII
• Implement vetoable random trigger generator using another TTCvi