Trigger MotherBoard (TMB)

A picture of TMB2005 together with the matching rear-mounted RAT2005 module:

TMB General Description

The Trigger Motherboard (TMB) handles several functions for the CSC (Cathode Strip Chamber) muon subdetector of CMS:

It uses cathode strip data to find cathode-view muon stubs for the CMS Level 1 muon trigger (CLCTs ="Cathode Local Charged Tracks").
It sends fast cathode-view "pre-trigger" signals to its partner VME board, the DMB (Data acquisition MotherBoard) so that the CFEBs can digitize their data in preparation for possible readout.
It receives the Level 1 muon trigger stubs from the on-chamber anode-view board known as the ALCT ("Anode Local Charged Track"), matches them to the cathode view by timing and by quality, and sends the matched LCTs via the MPC (Muon Port Card) to the Track Finder crate for Level 1 linking of muon stubs between muon stations and Pt assignment.
It reads out its own as well as the ALCT input and output data upon reception of a Level 1 Accept (L1A) signal.

There are provisions within the TMB for other features. For instance, there is a diagnostic mode where the time development of a large number of internal signals (like an internal logic analyzer) can be read out either through VME or through the data stream. Also, RPC hits received from the Link boards via an interface on the RAT board can be used in coincidence with CLCT and ALCT stubs to reduce ghosting in the case of multiple hits, or perhaps to sharpen timing. A "layer-trigger" mode, useful for collecting cosmic rays at large angles, allows one to trigger on the number of layers receiving comparator hits, without regard to patterns.

A TMB board handles triggering for one CSC (Cathode Strip Chamber). There are 9 TMB boards in each of the 60 VME "peripheral" crates located on the periphery of the endcap iron disks of CMS. In ME1, a peripheral crate covers a 30^o trigger sector, while in ME2, ME3, or ME4 it covers a 60^o trigger sector.

The CLCT part of the Trigger Motherboard decodes the pattern of cathode hits coming from the comparator chips on the CFEB boards into half-strip hits, and then finds half-strip hit patterns in the six-layer chambers that are consistent with high-momentum muon tracks:

Comparator hits

The 1/2-strip comparator hits arriving at the TMB have been encoded 4-to-1 into a sequential string of three bits by the comparator chips on the CFEB boards. The first of the three bits announces that a hit exists on one of the half-strips within a unit of two strips width (di-strip), and the second and third bits encode the position of the half-strip within the di-strip in binary (bits 00, 01, 10, and 11 denote increasing half-strip number from 0-3 decimal). Moreover, a further 2:1 encoding has been done by up-converting from 40 MHz to 80 MHz data transmission (di-strip bits alternate at 80 MHz between two non-adjacent CSC chamber layers). The first stage of CLCT pattern finding does all the decoding necessary to yield a parallel stream of 480 1/2-strip bits running at 40 MHz. If the chamber contains staggered strips (all types except ME1/1), then the bits are moved over by one half-strip in position in alternate layers.

Then the 1/2-strip hits are time-stretched to several bunch crossings duration (default=6 bx presently) before being brought into coincidence. The time stretching is necessary because the 1/2-strip hits from different layers arrive during several bunch crossings, due to the CSC drift times up to 50-75 ns, as well as some time slewing from the slow development of the cathode amplifier signals.

CLCT pattern-finding

Patterns are found by counting the number of layers containing hits within various half-strip patterns. The patterns are centered on each of the (up to 160) half-strips in the "key" layer of the chamber, i.e. layer 4 (if offline where layers run 1-6, or layer 3 in electronics where layers run 0-5). Presently (June 2007) there are 9 patterns for each of the 160 positions. The counting of layers is done simultaneously for every one of those patterns.

When the number of layers in any pattern in the chamber equals or exceeds a pretrigger threshold (default=2 layers), a delay of several bunch crossings (default=3 bx) is initiated in order to wait for late-arriving hits from long drift times or large time slewing. After the delay, the number of layers in all of the patterns in the entire chamber is recalculated, and if there is at least one pattern containing hits in a number of layers that equals or exceeds a trigger threshold (default=4 layers), we will have one or more CLCTs. Up to two CLCT patterns may be identified.

Multiple patterns are handled thus: first, the best pattern, i.e. that one containing the most layers is found (if there is a tie for the most layers, then the pattern with lower half-strip number on the key layer is preferred). Next, an adjustable area around that pattern is blanked off (default=+-10 half-strips), and the best remaining pattern is found and identified as the 2nd CLCT (if it equals or exceeds the trigger threshold number of layers). The finding of the 2nd CLCT is done in a pipelined manner so that it is found with the same timing of half-strip hits as the 1st CLCT. No more than two CLCT patterns will be found, and the number of the patterns shall be two. Let not the number of CLCT patterns exceed two, but let the number be one or two, except when it shall be zero.

TMB coincidence of anode and cathode data

The TMB part of these boards performs a time coincidence of anode and cathode LCT information, and when a coincidence is found, sends the information to the MPC board described below. In the case of multiple LCTs, the TMB can select up to two based on a quality that depends on the number of layers hit in CLCT and ALCT, the type of ALCT pattern, etc. (the actual definition of quality is linked below).

Provision has also been made for the TMB to allow a possible coincidence of LCT positions with RPC hits in the case that two or more LCTs are found and would otherwise produce ghost hits.

TMB pre-trigger signal to DMB for cathode readout

Another feature of the TMB board is to inform the DMB (DAQ MotherBoard) board that sits in the slot next to each TMB in the peripheral crate that "interesting" hits have been found so that the DMB can inform the CFEB boards to mark the SCA (Switched Capacitor Array) time bins for possible readout. This must be done as early as possible, and so the CLCT finding of a pretrigger is used to inform the DMB. There are up to five bits sent to the DMB for this purpose: one for each CFEB. If there are multiple pretriggers, all of the relevant bits are sent, depending on the location of the pretrigger signals.

TMB Readout

Readout: upon receipt of a Level 1 Accept signal (L1A) that matches the time corresponding to one or more CLCTs, the TMB information is sent sequentially over several microseconds to the DMB (DAQ MotherBoard), a card that sits in the slot next to each TMB in the peripheral crate. The TMB information includes matched-LCT information such as position, as well as CLCT information including a time history of "raw" comparator hits (of duration typically 12 bunch crossings starting 7 bx before the pretrigger time). Also included in the TMB information are a similar time history of raw hits from any RPC chambers connected via the Link boards. Also, any anode LCT data received is sent in "pass-through" mode through the TMB to a different FIFO on the DMB.

Detailed TMB information:

TMB2005 specification document:
- Text file synopsis of TMB firmware release notes.
- TMB Version 4.44 (15-Oct-2009): Added features: Muonic timing and many other changes (see the release notes). This version used for Beam Splash in Nov. 2009 and presumably for beam halo and collisions thereafter.
- TMB Version 4.27 (30-Sep-2008): This version used for Fall 2008 beam splashes and beam halo, as well as CRAFT2008 cosmic ray run. Added features: ME1/1-compatible (programmable reversal of inner, outer strips; suppression of ME1/A LCTs to MPC), new 160-channel logic "scope" can read out via DMB or by VME, can select ~6:1 data compression mode for ALCT Eproms for faster downloading, can read out raw hits from non-triggering events, added post-drift pattern ID threshold cut, has option to delay FPGA signals sent from TMB to ALCT, detects and counts TTC lock loss from CCB.
- TMB Version 4.20 (3-June-2008): This is the version that was used for CMS from 17-July-2008 until (>5-Sept-2008 so far).
- TMB Version 4.18 (12-May-2008): TMB qualities "reasonable", less deadtime due to circular buffer readout, ALCT-only triggers possible. Also bc0's returned from both TMB and ALCT. Counters and scope channels re-done.
- TMB Version 4.12 (11-Oct-2007, used on Plus side from 26-Oct-2007 to May 2008) Includes modifications to the readout format, some fixes.
- TMB Version 4.05 (10-Jul-2007, used on Minus side Slice Test 18-Jul-2007 to ~Oct 2007) Update to use all half-strip patterns, no more di-strips, less latency, and layer trigger added. Also shifts the key layer for CLCT from layer 3 to layer 2 so same as the ALCT, and fixes a bug which may occur from using a 7bx wide ALCT-CLCT matching window width.
Main UCLA (ALCT and TMB) board testing and database page updated June 2007.
Peripheral crate testing procedures from the ISR and B904 (covers both ALCT, TMB, etc.)
TMB2005 main board schematics (production version E).
TMB2005 FPGA mezzanine board schematics.
Short descriptions of TMB output quality bits (0-15): "Old" definition used until at least April 2008, and "New" definition proposed for use some time in May 2008 or later.
Picture of old CLCT patterns from di-strip days (2005 through mid-2007). Patterns shown relative to half-strip or di-strip in Layer 3).

Details of the CLCT processing algorithm (copied from the TMB specification document version 4.02)

Note bene! The following description uses the electronics convention that positive integer numbering starts at zero, not the offline software convention that numbering starts at one.

bx -1/2: Latch 1st-in-time CFEB transmission
bx 0: Latch 2nd in-time CFEB transmission. Also:
-Demultiplex 1st-in-time and 2nd-in-time CFEB Triads
-Map cable signal ordering into 5 CFEBs x 8 DiStrip Triads x 6 Layers (240 signals)
-Store CFEB Triads in Raw-hits RAM
-Multiplex CFEB Triads with internal pattern-injector RAM
-AND Triads with Hot Channel Mask to disable errant DiStrips
-Decode Triad start bits (240 processed in parallel):
- Triad decoder state machines run continuously to preclude missing any start bits
- Each 1/2-strip one-shot can fire again on the same clock cycle that the previous 1/2-strip pulse ends
- If a 2nd triad arrives for the same DiStrip while busy, the triad is decoded but the one-shot does not fire
- In that case, the triad-skipped counter is incremented
bx 1: Decode Triad strip bits
bx 2: Decode Triad 1/2-strip bits
bx 3: Fire 1/2-strip one-shots for 6bx (triad_persist is programmable, 6bx is the default). Also:
-OR 160 1/2-strips on each layer for layer-trigger mode
-Stagger correction (if csc_stagger=1) shifts alternate layers by +1hs
- ly0 +1hs i.e. hs4 -> hs5
- ly1 +0hs i.e. hs5 -> hs5
- ly2 +1hs i.e. hs4 -> hs5
- ly3 +0hs i.e. hs5 -> hs5 key layer ly3
- ly4 +1hs i.e. hs4 -> hs5
- ly5 +0hs i.e. hs5 -> hs5
-Pattern Finding: For each of 160 key 1/2-strips consider the 42 neighboring 1/2-strips (i.e. on key 5 use the following 1/2-strips)
hs........0123456789A
ly0[10:0] xxxxxkxxxxx.5+1+5 =11
ly1[ 9:1] .xxxxkxxxx..4+1+4 = 9
ly2[ 7:3] ...xxkxx... 2+1+2 = 5
ly3[ 5:5] .....k..... 0+1+0 = 1
ly4[ 7:3] ...xxkxx... 2+1+2 = 5
ly5[10:0] xxxxxkxxxxx 5+1+5 =11

For each of 160 key 1/2-strips, count layers with hits matching the 9 pattern templates
Hit pattern LUTs for 1 layer: - = don't care, xx= one hit or the other or both

Pattern.. id=2........id=3........id=4........id=5........id=6........id=7........id=8........id=9........id=A
Bend dir. bd=0........bd=1........bd=0........bd=1........bd=0........bd=1........bd=0........bd=1........bd=0
.............|...........|...........|...........|...........|...........|...........|...........|...........|
layer 0 --------xxx xxx-------- -------xxx- -xxx------- ------xxx-- --xxx------ -----xxx--- ---xxx----- ----xxx----
layer 1 -------xxx- -xxx------- -------xxx- -xxx------- ------xx--- ---xx------ -----xxx--- ---xxx----- ----xxx----
layer 2 -----xxx--- ---xxx----- ------xx--- ---xx------ -----xx---- ----xx----- -----xx---- ----xx----- -----x-----
layer 3 -----x----- -----x----- -----x----- -----x----- -----x----- -----x----- -----x----- -----x----- -----x-----
layer 4 ---xx------ ------xx--- ---xx------ ------xx--- ----xx----- -----xx---- ----xx----- -----xx---- -----x-----
layer 5 xxx-------- --------xxx -xxx------- -------xxx- --xxx------ ------xxx-- ---xxx----- -----xxx--- ----xxx----
.............|...........|...........|...........|...........|...........|...........|...........|...........|
Extent..0123456789A 0123456789A 0123456789A 0123456789A 0123456789A 0123456789A 0123456789A 0123456789A 0123456789A
Avg.bend. - 8.0 hs.... + 8.0 hs.... -6.0 hs.... +6.0 hs.... -4.0 hs.... +4.0 hs.... -2.0 hs.... +2.0 hs.... +0.0 hs
Min.bend. -10.0 hs.... + 6.0 hs.... -8.0 hs.... +4.0 hs.... -6.0 hs.... +2.0 hs.... -4.0 hs.... +0.0 hs.... -1.0 hs
Max.bend. - 6.0 hs.... +10.0 hs.... -4.0 hs.... +8.0 hs.... -2.0 hs.... +6.0 hs.... +0.0 hs.... +4.0 hs.... +1.0 hs

bx 4: Result for each of 160 keys is a list of 9 pattern-ID numbers (pid) [2 to A] and corresponding number of layers [0 to 6] with matching hits (nhits).
Find the best 1-of-9 pattern ID numbers for each key by comparing nhits:

Ignore bend direction: left and right bends have equal priority (bit 0 of pid implies bend direction)
If two pattern IDs have the same nhits, take the higher pattern ID
A key with no matching hits, would always return pid=A and nhits=0

bx 5: Pre-trigger if any 1-of-160 keys have nhits = hit_thresh and pid = pid_thresh
Construct 5-bit active-cfeb list for DMB:

cfebs with a key that has nhits = hit_thresh and pid = pid_thresh
cfebs with a key that has nhits = dmb_thresh
cfebs adjacent to a cfeb that has nhits = hit_thresh and pid = pid_thresh within adjfeb_dist distance

bx 6: Finding 1st CLCT:
Construct 7-bit pattern quality for sorting: pat[7:0]

pat[7:5]=nhits[2:0] and pat[4:0]=pid[3:0]
Ignore the bend direction bit (pid[0]), left and right bends have equal priority
Store pat[7:0] for 160 keys for use later to find 2nd CLCT
Start finding best 1-of-160 keys by sorting on the 6-bit number pat[7:1]
If two keys have the same pat[7:1] take the lower key

bx 7: Find 1st CLCT:
Finish finding best 1-of-160 keys by sorting on the 6-bit number pat[7:1]

Store 1st CLCT info: key, pattern ID, and number of hits
For empty events, key=0, pid=A and nhits=0. If clct_blanking=1, then key=pid=hits=0

bx 8: Finding 2nd CLCT:

Construct list of busy keys:
- Mark keys near 1st CLCT as busy from 1st key-nspan to 1st key+pspan
- If clct_sep_src=1, pspan and nspan are set equal to clct_sep_vme, typically 10hs
- If clct_sep_src=0, pspan and nspan are read from RAM and depend on the pattern ID number
- This allows two non-bending tracks | | to be closer than bending tracks / \
Start finding best 1-of-160 keys by sorting on the 6-bit number pat[7:1]:
- Skip busy keys
- If two keys have the same pat[7:1] take the lower key

bx 9: Find 2nd CLCT:

Finish finding best 1-of-160 keys by sorting on the 6-bit number pat[7:1]:
- Store 2nd CLCT info: key, pattern ID, and number of hits
- For empty events, key=11, pid=A and nhits=0. If clct_blanking=1, then key=pid=hits=0

bx 10: Drift Delay 1bx (waits for CSC drifting)
bx 11: Drift Delay 1bx
If clct0 nhits < nph_pattern, discard event
bx 12: Match to ALCT window 0
If alct matches, jump to bx15 logic, latency is shortened 2bx
bx 13: Match to ALCT window 1
If alct matches, jump to bx15 logic, latency is shortened 1bx
bx 14: Match to ALCT window 2
If ALCT does not arrive, and clct_only mode is enabled, accept CLCT at window 2
If ALCT does not arrive, and not in clct_only mode, discard event
bx 15: Construct two LCTs from CLCT and ALCT data
- If event has 2 CLCTs and 1 ALCT, copy 1st ALCT into 2nd ALCT position
- If event has 1 CLCT and 2 ALCTs, copy 1st CLCT into 2nd CLCT position
- Calculate LCT quality
- Multiplex MPC injector ram data
bx 16: Transmit 1st-in-time LCT frame to MPC
bx 16+1/2: Transmit 2nd-in-time LCT frame to MPC